1. Field of the Invention
The present invention relates to a column address strobe (CASB) circuit, and more particularly, to a CASB buffer circuit ensuring a stable writing operation even in the case where a casb signal has a narrow pulse width.
2. Discussion of Related Art
In semiconductor memory devices, in case of writing data in a memory cell, a writing enable signal web is at a low state only if a casb signal is at a low state for a predetermined time, for purpose of writing data in a memory cell. If the low state is only maintained for a short time due to the casb signal being of insufficient duration, the data writing operation with a writing enable signal web is interrupted or stopped short as the writing enable signal returns to a high state before the data can fully written in the memory cell. Accordingly, in such a case, a casb signal having a narrow pulse width generates an error in the writing operation and thus, the data cannot be stably written in the memory cell.
FIG. 1 is a circuit diagram of a conventional CASB buffer circuit. The conventional CASB buffer circuit includes an input means for inputting a casb signal, and an output means for receiving the casb signal and then outputting a casb signal.
The input means includes a first P type MOS transistor 11 having a gate for externally receiving an inverse power-up signal pwrupb; an inverter including a second P type MOS transistor 12 and first and second N type MOS transistors 13 and 14 having a gate for externally receiving an inverse cas signal casb; and an inverting gate 16 for inverting an output signal from the inverter.
The output means includes an inverting gate 18 for inverting an output signal of the inverting gate 16 and generating a first cas signal cas1; and additional inverting gates, 19-21, for inverting the output signal of the inverting gate 16 and generating a second cas signal cas2.
As illustrated in FIG. 1, the input means of the conventional CASB buffer circuit further includes a third N type MOS transistor 15 connected in parallel to the first N type MOS transistor 13, having a gate which receives an output signal of the inverting gate 16 to protect the inverting gates 16-21 in a case where the casb signal applied to the gate is above a predetermined voltage; and a fourth N type MOS transistor 17 having a drain connected to an output terminal of the inverter 16 and a gate for receiving an inverse power-up signal pwrupb.
Operation of the thus-structured conventional CASB buffer circuit will be described with reference to FIGS. 2A to 2G.
If an address addr is externally applied, as shown in FIG. 2A, and the rasb signals are "LOW", as shown in FIGS. 2B and 2C, thus selecting an X-address, namely, the row address, the casb signal is at an active-low state, as shown in FIG. 2D.
The first P type MOS transistor 12 is turned on by the casb signal, so that an output of the inverting gate 16 becomes LOW. Accordingly, the cas1 signal output through the inverting gate 18 becomes HIGH, as shown in FIG. 2E.
If the writing enable signal web becomes active LOW as shown in FIG. 2F to perform the writing operation, the we1 signal becomes HIGH as in FIG. 2G. When the we1 signal becomes HIGH while the web signal is at the active-low state, the data is written in the externally applied address.
As described above, the conventional CASB buffer circuit enables the cas1 to be HIGH by the casb signal during the writing operation, thus controlling the we1 signal. Therefore, if the we1 signal becomes HIGH, the writing operation is performed, and if it becomes LOW, the writing operation is stopped.
In short, the conventional CASB buffer circuit of a semiconductor memory device inputs the casb signal, delays it through the inverting gate and generates the cas1 signal. If, however, the applied casb signal has a narrow pulse width and thus maintains a low state for insufficient amount of time, in particular, for a page cycle having a short cycle rate, the writing enable signal web becomes HIGH before the data can be fully written in the designated address.